library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity pipeif is
	generic
	(
		DATA_WIDTH	: natural  :=	32
	);


	port
	(
		-- Input ports
		branch	: in  std_logic;
		pc : in std_logic_vector(DATA_WIDTH-1 downto 0);
		bpc : in std_logic_vector(DATA_WIDTH-1 downto 0);
		rom_clock : std_logic;
		-- Output ports
		npc : out std_logic_vector(DATA_WIDTH-1 downto 0);
		pc4 : out std_logic_vector(DATA_WIDTH-1 downto 0);
		ins : out std_logic_vector(DATA_WIDTH-1 downto 0)
	);
end pipeif;

architecture rtl_pipeif of pipeif is
component lpm_mux32
	PORT
	(
		data0x		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
		data1x		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
		sel		: IN STD_LOGIC ;
		result		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
	);
end component;

component lpm_rom0
	PORT
	(
		address		: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
		clock		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
	);
end component;

component vm
	port
	(
		-- Input ports
		vaddr	: in  std_logic_vector(DATA_WIDTH-1 downto 0);		
		-- Output ports
		maddr	: out std_logic_vector(DATA_WIDTH-1 downto 0)
	);	
end component;

signal pc4_inner,maddr : std_logic_vector(DATA_WIDTH-1 downto 0);
begin
	process (pc)
	begin
		pc4_inner <= pc + 4;
	end process;
	
	pc4<= pc4_inner;
	
	branch_mux : lpm_mux32 port map(
		data0x => pc4_inner,
		data1x => bpc,
		sel => branch,
		result => npc
	);
	
	translator: vm port map(
		vaddr => pc,
		maddr => maddr
	);
	
	instmem: lpm_rom0 port map(
		--address => pc(7 downto 2),
		address => maddr(7 downto 2),
		clock => rom_clock,
		q => ins
	);
end rtl_pipeif;

